Referring to FIG. 1, a conventional divide-by-three injection locked frequency divider (ILFD) includes a resonator circuit 11, a mixer circuit 12 and two buffers 13, and performs frequency division on an input voltage signal (Vinj) with an input frequency to generate a differential output voltage signal pair (Vout1, Vout2) with a frequency that is one-third the input frequency.
The resonator circuit 11, the mixer circuit 12 and the buffers 13 cooperate to form a tank circuit that has a free-running frequency and that defines a frequency locking range which is around three times the free-running frequency and within which the input frequency falls. The resonator circuit 11 includes two inductors 111. The mixer circuit 12 includes four transistors 121-124 and other elements, and mixes the input voltage signal (Vinj) with a differential reference voltage signal pair to generate a differential mixed voltage signal pair, where the differential reference voltage signal pair has a frequency that is twice a frequency of the differential mixed voltage signal pair, and where the frequency of the differential mixed voltage signal pair is one-third the input frequency. The buffers 13 cooperatively buffer the differential mixed voltage signal pair to generate the differential output voltage signal pair (Vout1, Vout2).
A width of the frequency locking range (1r) can be expressed by the following equation:
                              lr          ≈                                                    f                osc                                            2                ·                                  ∏                                      ·                    Q                                                                        ·                                          I                inj                                            I                dc                                      ·                                          α                2                                            α                1                                                    ,                            Equation        ⁢                                  ⁢        1            where fosc denotes the free-running frequency, Q denotes a quality factor of the conventional ILFD, Iinj denotes an injection current that flows into the conventional ILFD and that corresponds to the input voltage signal (Vinj), Idc denotes a total DC bias current that is required by the transistors 121-124 and that is a sum of drain currents of the transistors 121-124, α1 denotes a small signal conversion gain of each of the transistors 121, 122, and α2 denotes a small signal second order term coefficient that reflects second order nonlinearity of each of the transistors 121, 122.
For the conventional ILFD, the free-running frequency (fosc) is low and the small signal second order term coefficient (α2) is small, so the frequency locking range is narrow. Although the total DC bias current (Idc) can be increased to thereby increase the small signal second order term coefficient (α2) and thus the width of the frequency locking range (lr), the increase of the total DC bias current (Idc) also leads to decrease of the width of the frequency locking range (lr) and increase of power consumption of the conventional ILFD. As a consequence, the width of the frequency locking range (lr) is increased slightly, but the power consumption is increased significantly.